dc.contributor.author |
Arlı, A. Çağrı
|
|
dc.contributor.author |
Çolak, Ayşe
|
|
dc.contributor.author |
Gazi, Orhan
|
|
dc.date.accessioned |
2020-03-20T07:43:20Z |
|
dc.date.available |
2020-03-20T07:43:20Z |
|
dc.date.issued |
2017 |
|
dc.identifier.citation |
Arlı, A.Çağrı; Çolak, Ayşe; Gazi, Orhan, "The implementation of a successive cancellation polar decoder on xilinx system generator", 2017 24th IEEE International Conference On Electronics, Cıicuits And Systems (ICECS), pp.372-376, (2017). |
tr_TR |
dc.identifier.isbn |
978-1-5386-1911-7 |
|
dc.identifier.uri |
http://hdl.handle.net/20.500.12416/2705 |
|
dc.description.abstract |
Polar coding is the first kind of the capacity achieving codes which are defined for binary-input discrete memoryless channels initially. Parallel processing property of the FPGA allows to decode faster with a margin of complexity. Xilinx System Generator as a practical tool to construct decoding designs in shorter time is a fact. In this study, FPGA implementation of decoding polar codes through Xilinx System Generator is shown. |
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dc.language.iso |
eng |
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dc.publisher |
IEEE |
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dc.rights |
info:eu-repo/semantics/closedAccess |
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dc.subject |
Coding Theory |
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dc.subject |
FPGA |
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dc.subject |
Paralel Decoding |
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dc.title |
The implementation of a successive cancellation polar decoder on xilinx system generator |
tr_TR |
dc.type |
conferenceObject |
tr_TR |
dc.relation.journal |
2017 24th IEEE International Conference On Electronics, Cıicuits And Systems (ICECS) |
tr_TR |
dc.contributor.authorID |
206005 |
tr_TR |
dc.contributor.authorID |
102896 |
tr_TR |
dc.identifier.startpage |
372 |
tr_TR |
dc.identifier.endpage |
376 |
tr_TR |
dc.contributor.department |
Çankaya Üniversitesi, Mühendislik Fakültesi, Elektronik ve Haberleşme Mühendisliği Bölümü |
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