dc.contributor.author |
Aktaş, Hakan
|
|
dc.contributor.author |
Sever, Refik
|
|
dc.contributor.author |
Töreyin, Behçet Uğur
|
|
dc.date.accessioned |
2020-04-19T23:53:12Z |
|
dc.date.available |
2020-04-19T23:53:12Z |
|
dc.date.issued |
2015 |
|
dc.identifier.citation |
Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015). |
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dc.identifier.issn |
2165-0608 |
|
dc.identifier.uri |
http://hdl.handle.net/20.500.12416/3379 |
|
dc.description.abstract |
In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. |
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dc.language.iso |
eng |
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dc.publisher |
IEEE |
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dc.rights |
info:eu-repo/semantics/closedAccess |
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dc.subject |
Template Matching |
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dc.subject |
Sum of Absolute Differences |
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dc.subject |
Field-Programmable-Gate-Array (FPGA) |
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dc.subject |
Parallel Processing |
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dc.subject |
Memory Adressing |
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dc.subject |
Unmanned Air Vehicle (UAV) |
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dc.title |
A Two Stage Template Matching Algorithm and Its Implementation on FPGA |
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dc.type |
conferenceObject |
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dc.relation.journal |
23nd Signal Processing and Communications Applications Conference (SIU) |
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dc.contributor.authorID |
19325 |
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dc.identifier.startpage |
2214 |
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dc.identifier.endpage |
2217 |
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dc.contributor.department |
Çankaya Üniversitesi, Mühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümü |
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