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A Two Stage Template Matching Algorithm and Its Implementation on FPGA

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dc.contributor.author Aktaş, Hakan
dc.contributor.author Sever, Refik
dc.contributor.author Töreyin, Behçet Uğur
dc.date.accessioned 2020-04-19T23:53:12Z
dc.date.available 2020-04-19T23:53:12Z
dc.date.issued 2015
dc.identifier.citation Toreyin, Behcet Ugur; Aktas, Hakan; Sever, Refik, "A Two Stage Template Matching Algorithm and Its Implementation on FPGA", 23nd Signal Processing and Communications Applications Conference (SIU), pp. 2214-2217, (2015). tr_TR
dc.identifier.issn 2165-0608
dc.identifier.uri http://hdl.handle.net/20.500.12416/3379
dc.description.abstract In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs. tr_TR
dc.language.iso eng tr_TR
dc.publisher IEEE tr_TR
dc.rights info:eu-repo/semantics/closedAccess tr_TR
dc.subject Template Matching tr_TR
dc.subject Sum of Absolute Differences tr_TR
dc.subject Field-Programmable-Gate-Array (FPGA) tr_TR
dc.subject Parallel Processing tr_TR
dc.subject Memory Adressing tr_TR
dc.subject Unmanned Air Vehicle (UAV) tr_TR
dc.title A Two Stage Template Matching Algorithm and Its Implementation on FPGA tr_TR
dc.type conferenceObject tr_TR
dc.relation.journal 23nd Signal Processing and Communications Applications Conference (SIU) tr_TR
dc.contributor.authorID 19325 tr_TR
dc.identifier.startpage 2214 tr_TR
dc.identifier.endpage 2217 tr_TR
dc.contributor.department Çankaya Üniversitesi, Mühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümü tr_TR


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